Bipolar transistors are extensively used for high speed switching in integrated circuits. To improve speed of the transistor, the device dimensions are being shrunk both horizontally and vertically. The vertical bipolar transistors, most commonly used in ICs, have vertically aligned emitter, base and collector regions (Ning et al., Self-Aligned Bipolar transistors for High Performance and Low power delay VLSI" IEEE Trans. Elec. Dev. ED-28, pps. 1010-1013, 1981). FIG. 1 shows a cross section of an NPN bipolar transistor with the collector 12, base 14 and emitter 16 on a substrate 10. Also shown in FIG. 1, are deep trench isolation 18, shallow trench isolation 20, extrinsic base 22, subcollector 24, collector reach-through 26, the base-collector junction 28 and the emitter-base junction 30. The emitter and the collector are doped with phosphorous or arsenic (N dopants) and the base is doped with boron (P type).
An important feature in a bipolar transistor is the characteristics of the emitter-base junction, which is the transition region in the silicon, where the high N dopant concentration of the emitter and the high P dopant concentration of the base cross over. A narrow emitter-base junction has been claimed to improve current gain of the transistor by improving the emitter injection efficiency (M. Kondo, M. Namba, T. Kobayashi, S. Iijima and T. Nakamura, VLSI 91 Proceedings, pps. 65-66). A narrow emitter-base junction is known to speed up the switching by reducing the base transit time and the emitter charge storage time.
Another important feature is the base-collector junction, which is the base to collector transition region. A third important feature is the width of the base layer, i.e, the P dopant region between the emitter and the collector.
The ability to control the junction profile allows one to control the base width predictably. The base width control is improved by the ability of the process to make abrupt emitter-base and base-collector junctions.
Another important consideration is low electrical contact resistance, especially since emitter dimensions are small. In the case of polysilicon emitters, the contact between polysilicon and the single crystal silicon defined by the emitter opening must preferably have low resistance.
It is well known from prior art that in the manufacture of bipolar devices, epitaxial deposition methods are used extensively to deposit monocrystalline layers that are defined to form sub-collector, collector and base regions. Also ion implantation and high temperature annealing are used to dope the base, extrinsic base, emitter and reach-through regions and to activate and control dopant profiles. These processes are not reviewed here in any detail. However, an aspect of semiconductor processing relevant to the present invention is the process of depositing amorphous and poly-Si and recrystallizing them by Solid Phase Epitaxy.
U.S. Pat. No. 4,565,584 to Tamura et al. shows a method of producing a single crystal film by first depositing a pattern of insulating material over a single crystal substrate. An amorphous or polycrystalline film is formed over both the insulator and exposed areas of the substrate. The structure is then annealed to convert the amorphous or polycrystalline film by solid phase epitaxy (SPE) into a monocrystalline structure.
Kunii, Y., et al., "Solid-Phase Lateral Epitaxy of Chemical-Vapor-Deposited Amorphous Silicon by Furnace Annealing", J. Appl. Phys., 54 (5), May 1983, pps. 2847-2850, shows a similar process for SPE growth of monocrystalline silicon over silicon/insulator using a two step anneal. A layer of amorphous silicon is first annealed at a temperature in the range of 550.degree.-650.degree. C. to effect crystalline growth, and second annealed in the range of about 1150.degree. C. to reduce dislocations.
U.S. Pat. No. 3,900,345 to Lesk shows a process for forming thin epitaxial regions by first forming a layer of amorphous silicon over a layer of single crystal (i.e. monocrystalline) silicon. Ions are implanted to cause defects at the amorphous/monocrystalline interface and cause a more intimate contact. The structure is then annealed at a temperature in the range of 600.degree.-900.degree. C. to convert the amorphous silicon by SPE to single crystal silicon.
Japanese Patent No. 62-48014 by Sony Corp. shows a process wherein a thin film of polysilicon is formed over a monocrystalline silicon substrate. Ions are implanted to make the polycrystalline amorphous. A thicker layer of amorphous silicon is formed over the first layer. The structure is then subjected to a low temperature anneal (of about 600.degree. C.) to convert the two layers of amorphous silicon by SPE to a thick layer of single crystal silicon.
The following patents show the use of SPE to form transistor device regions.
U.S. Pat. Nos. 4,812,890 and 4,651,410, both to Feygenson, show a method of forming a bipolar transistor wherein both the base and collector regions are formed by recrystallization (at about 800.degree. C.) of polysilicon. The base and collector regions are separately doped, after each region is recrystallized, to the desired dopant concentration. The process suffers from several disadvantages. First, the recrystallization of polysilicon requires a relatively high-temperature anneal, sufficient to cause some undesirable dopant diffusion. Further, the doping of the base and collector regions after recrystallization provides a poor control on the dopant profiles and the characteristics of the junctions.
U.S. Pat. No. 4,853,342 to Taka et al. shows a method of forming a bipolar transistor wherein selective SPE of polysilicon is performed twice, once to form a collector region and once to form a base region. Each recrystallization is performed at a temperature of about 550.degree. C. Multiple implants are performed prior to each recrystallization: to provide dopant impurities, and to "clean" the mono-polycrystalline interface. This method also suffers from the disadvantages of subsequent doping of the recrystallized regions results, discussed earlier.
U.S. Pat. No. 4,789,644 to Meda shows a process of forming an insulated gate field-effect transistor (IGFET) wherein polysilicon is deposited over single crystal silicon, ions are selectively implanted through the polysilicon and into the single crystal silicon so as to render the polysilicon amorphous. Recrystallization heat treatment is then performed at temperatures of between 450.degree.-600.degree. C. to recrystallize the implanted, amorphous silicon by SPE as single crystal silicon. These recrystallized regions comprise the source and drain, respectively, of the IGFET.
Zhu, E., "Amorphous Si/Si Heterojunction Microwave Transistors," IEEE Electron Device Letters, Vol 10, No. 1, January 1989, pps. 4-6, discusses the formation of a heterojunction bipolar transistor wherein low-temperature, plasma-enhanced chemical vapor deposition (PECVD) is used to form an amorphous silicon emitter. This process results in high emitter resistance.
Another example wherein low temperature processes are beneficially used is that of forming heterojunction bipolar transistors (HBT). For a description of an HBT, see Patton, G. L., et al., "Silicon-Germanium-Base Heterojunction Bipolar Transistors by Molecular Beam Epitaxy", IEEE Electron Device Letters, Vol. 9, No. 4, April 1988, pps. 165-167. In the above mentioned device, very thin base region is formed using molecular beam epitaxy (MBE) at temperatures below about 550.degree. C. However, no practical, bulk manufacturing process is known using MBE base.
Processes for forming HBT transistors are known wherein ultra-thin base regions are formed using the ultrahigh vacuum chemical vapor deposition (UHV/CVD) process shown, for example, in Meyerson, B. S., et al. "Low Temperature Silicon Epitaxy by Hot Wall Ultrahigh Vacuum/Low pressure Chemical Vapor Deposition Techniques: Surface Optimization", J. Electrochem. Soc.: Solid-State Science and Technology, Vol. 133, No. 6, pps. 1232-1235. However, such processes have suggested the use of a higher temperature process to form the emitter region. Such a high temperature can cause boron diffusion leading to increase in base width. It can also cause dislocations to form in the strained Si-Ge layer, resulting in degradation of transistor characteristics and yield.
In fact, no acceptable process for bulk manufacturing transistors, particularly HBT transistors, is known to the present inventors which includes a low temperature process for forming the transistor emitter. As mentioned above, known processes which utilize UHV/CVD to form ultrathin base regions have utilized high temperature emitter fabrications. In specific, the low temperature used (less than 700.degree. C.) in these processes are beneficial for fabricating very narrow base width (500 .ANG. to 2000 .ANG.) devices.
U.S. Pat. No. 4,523,370 issued to Sullivan and Collins, June 1985 claims process improvements to achieve narrow base widths and abrupt base-collector and base-emitter junctions. In his process, he deposits a polysilicon base layer with an in-situ doping at low temperature over the single crystal collector region, and converts the polycrystalline region to single crystal by annealing at about 1200.degree. C. for 10 seconds, thereby converting the polycrystal into single crystal by solid phase epitaxy. This has been claimed to establish a sharp collector-base junction.